Conductor reservoir volume for integrated circuit interconnects

ABSTRACT

An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A first dielectric layer on the device dielectric layer has an opening formed therein including a conductor reservoir volume. A barrier layer lines the channel opening. A conductor core fills the opening over the barrier layer. A second dielectric layer is formed on the first dielectric layer and has a second channel and via opening provided therein. A barrier layer lines the second channel and via opening except over the first channel opening. A conductor core fills the second channel and via opening over the barrier layer and the first conductor core to form the second channel and via. The conductor reservoir volume provides a supply of conductor material to prevent the formation of voids in the first channel and in the via.

TECHNICAL FIELD

[0001] The present invention relates generally to semiconductortechnology and more specifically to preventing interconnect voids insemiconductor devices.

BACKGROUND ART

[0002] In the manufacture of integrated circuits, after the individualdevices such as the transistors have been fabricated in and on thesemiconductor substrate, they must be connected together to perform thedesired circuit functions. This interconnection process is generallycalled “metallization” and is performed using a number of differentphotolithographic, deposition, and removal techniques.

[0003] In one interconnection process, which is called a “dualdamascene” technique, two channels of conductor materials are separatedby interlayer dielectric layers in vertically separated planesperpendicular to each other and interconnected by a vertical connection,or “via”, at their closest point. The dual damascene technique isperformed over the individual devices which are in a device dielectriclayer with the gate and source/drain contacts, extending up through thedevice dielectric layer to contact one or more channels in a firstchannel dielectric layer.

[0004] The first channel formation of the dual damascene process startswith the deposition of a thin first channel stop layer. The firstchannel stop layer is an etch stop layer which is subject to aphotolithographic processing step which involves deposition, patterning,exposure, and development of a photoresist, and an anisotropic etchingstep through the patterned photoresist to provide openings to the devicecontacts. The photoresist is then stripped. A first channel dielectriclayer is formed on the first channel stop layer. Where the first channeldielectric layer is of an oxide material, such as silicon oxide (SiO₂),the first channel stop layer is a nitride, such as silicon nitride(SiN), so the two layers can be selectively etched.

[0005] The first channel dielectric layer is then subject to furtherphotolithographic process and etching steps to form first channelopenings in the pattern of the first channels. The photoresist is thenstripped.

[0006] An optional thin adhesion layer is deposited on the first channeldielectric layer and lines the first channel openings to ensure goodadhesion of subsequently deposited material to the first channeldielectric layer. Adhesion layers for copper (Cu) conductor materialsare composed of compounds such as tantalum nitride (TaN), titaniumnitride (TiN), or tungsten nitride (WN).

[0007] These nitride compounds have good adhesion to the dielectricmaterials and provide good barrier resistance to the diffusion of copperfrom the copper conductor materials to the dielectric material. Highbarrier resistance is necessary with conductor materials such as copperto prevent diffusion of subsequently deposited copper into thedielectric layer, which can cause short circuits in the integratedcircuit.

[0008] However, these nitride compounds also have relatively pooradhesion to copper and relatively high electrical resistance.

[0009] Because of the drawbacks, pure refractory metals such as tantalum(Ta), titanium (Ti), or tungsten (W) are deposited on the adhesion layerto line the adhesion layer in the first channel openings. The refractorymetals are good barrier materials, have lower electrical resistance thantheir nitrides, and have good adhesion to copper.

[0010] In some cases, the barrier material has sufficient adhesion tothe dielectric material that the adhesion layer is not required, and inother cases, the adhesion and barrier material become integral. Theadhesion and barrier layers are often collectively referred to as a“barrier” layer herein.

[0011] For conductor materials such as copper, which are deposited byelectroplating, a seed layer is deposited on the barrier layer and linesthe barrier layer in the first channel openings. The seed layer,generally of copper, is deposited to act as an electrode for theelectroplating process.

[0012] A first conductor material is deposited on the seed layer andfills the first channel opening. The first conductor material and theseed layer generally become integral, and are often collectivelyreferred to as the conductor core when discussing the maincurrent-carrying portion of the channels.

[0013] A chemical-mechanical polishing (CMP) process is then used toremove the first conductor material, the seed layer, and the barrierlayer above the first channel dielectric layer to form the firstchannels. When a layer is placed over the first channels as a finallayer, it is called a “cap” layer and a “single” damascene process iscompleted. When the layer is processed further for placement ofadditional channels over it, the layer is a via stop layer.

[0014] The via formation step of the dual damascene process starts withthe deposition of a thin via stop layer over the first channels and thefirst channel dielectric layer. The via stop layer is an etch stop layerwhich is subject to photolithographic processing and anisotropic etchingsteps to provide openings to the first channels. The photoresist is thenstripped.

[0015] A via dielectric layer is formed on the via stop layer. Again,where the via dielectric layer is of an oxide material, such as siliconoxide, the via stop layer is a nitride, such as silicon nitride, so thetwo layers can be selectively etched. The via dielectric layer is thensubject to further photolithographic process and etching steps to formthe pattern of the vias. The photoresist is then stripped.

[0016] A second channel dielectric layer is formed on the via dielectriclayer. Again, where the second channel dielectric layer is of an oxidematerial, such as silicon oxide, the via stop layer is a nitride, suchas silicon nitride, so the two layers can be selectively etched. Thesecond channel dielectric layer is then subject to furtherphotolithographic process and etching steps to simultaneously formsecond channel and via openings in the pattern of the second channelsand the vias. The photoresist is then stripped.

[0017] An optional thin adhesion layer is deposited on the secondchannel dielectric layer and lines the second channel and the viaopenings.

[0018] A barrier layer is then deposited on the adhesion layer and linesthe adhesion layer in the second channel openings and the vias.

[0019] Again, for conductor materials such as copper and copper alloys,which are deposited by electroplating, a seed layer is deposited byelectroless deposition on the barrier layer and lines the barrier layerin the second channel openings and the vias.

[0020] A second conductor material is deposited on the seed layer andfills the second channel openings and the vias.

[0021] A CMP process is then used to remove the second conductormaterial, the seed layer, and the barrier layer above the second channeldielectric layer to form the first channels. When a layer is placed overthe second channels as a final layer, it is called a “cap” layer and the“dual” damascene process is completed.

[0022] The layer may be processed further for placement of additionallevels of channels and vias over it.

[0023] The use of the single and dual damascene techniques eliminatesmetal etch and dielectric gap fill steps typically used in themetallization process. The elimination of metal etch steps is importantas the semiconductor industry moves from aluminum (Al) to othermetallization materials, such as copper, which are very difficult toetch.

[0024] A major problem occurs with interconnects at the interconnectionof the channels with the vias. When current flow through theinterconnect causes internal electromigration of copper from the via,the copper is not made up from the channel because of the barrier layerwhich prevents copper diffusion between the channel and the via aboveit, and this leads to voids in the via which leads to integrated circuitfailure over time.

[0025] If the barrier layer is eliminated between the channel and thevia above it, voids could form in the channel which also lead tointegrated circuit failure over time.

[0026] A solution to this problem has been long sought but has longeluded those skilled in the art.

DISCLOSURE OF THE INVENTION

[0027] The present invention provides an integrated circuit having asemiconductor substrate with a semiconductor device. A first dielectriclayer is on the semiconductor substrate and has a first channel openingprovided therein. The first channel opening is provided with a channelreservoir volume. A barrier layer lines the first channel opening, and afirst conductor core fills the first channel opening over the barrierlayer to form a first channel. A second dielectric layer is formed onthe first dielectric layer and has a second channel and via openingprovided therein. A barrier layer lines the second channel and viaopening except over the first channel opening. A conductor core fillsthe second channel and via opening over the barrier layer and the firstconductor core to form the second channel and via. The conductorreservoir volume provides a supply of conductor material to prevent theformation of voids in the first channel and in the via.

[0028] The present invention further provides a method for manufacturingan integrated circuit having a semiconductor substrate with asemiconductor device. A first dielectric layer is formed on thesemiconductor substrate and has a first channel opening formed therein.The first channel opening is formed with a channel reservoir volume. Abarrier layer lines the first channel opening, and a first conductorcore fills the first channel opening over the barrier layer and both areremoved over the first dielectric layer to form a first channel. Asecond dielectric layer is formed on the first dielectric layer and hasa second channel and via opening formed therein. A barrier layer linesthe second channel and via opening. The barrier layer in the via openingover the first channel opening is removed and a conductor core fills thesecond channel and via opening over the barrier layer and the firstconductor core. The barrier layer and the conductor core are removedover the second dielectric layer to form the second channel and via. Theconductor reservoir volume provides a supply of conductor material toprevent the formation of voids in the first channel and in the viaduring operation.

[0029] The present invention can also be used with a single damasceneprocess as well as a dual damascene process.

[0030] The above and additional advantages of the present invention willbecome apparent to those skilled in the art from a reading of thefollowing detailed description when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0031]FIG. 1 (PRIOR ART) is a plan view of aligned channels with aconnecting via;

[0032]FIG. 2 (PRIOR ART) is a cross-section of FIG. 1 along line 2-2;and

[0033]FIG. 3 is a cross-section similar to FIG. 2 (PRIOR ART) showingthe conductor reservoir volume according to the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

[0034] Referring now to FIG. 1 (PRIOR ART), therein is shown a plan viewof a semiconductor wafer 100 having as interconnects first and secondchannels 102 and 104 connected by a via 106. The first and secondchannels 102 and 104 are respectively disposed in first and seconddielectric layers 108 and 110. The via 106 is an integral part of thesecond channel 104 and is disposed in a via dielectric layer 112.

[0035] The term “horizontal” as used in herein is defined as a planeparallel to the conventional plane or surface of a wafer, such as thesemiconductor wafer 100, regardless of the orientation of the wafer. Theterm “vertical” refers to a direction perpendicular to the horizontal asjust defined. Terms, such as “on”, “above”, “below”, “side” (as in“sidewall”), “higher”, “lower”, “over”, and “under”, are defined withrespect to the horizontal plane.

[0036] Referring now to FIG. 2 (PRIOR ART), therein is shown across-section of FIG. 1 (PRIOR ART) along line 2-2. A portion of thefirst channel 102 is disposed in a first channel stop layer 114 and ison a device dielectric layer 116. Generally, metal contacts are formedin the device dielectric layer 116 to connect to an operativesemiconductor device (not shown). This is represented by the contact ofthe first channel 102 with a semiconductor contact 118 embedded in thedevice dielectric layer 116. The various layers above the devicedielectric layer 116 are sequentially: the first channel stop layer 114,the first channel dielectric layer 108, a via stop layer 120, the viadielectric layer 112, a second channel stop layer 122, the secondchannel dielectric layer 110, and a next channel stop layer 124 (notshown in FIG. 1).

[0037] The first channel 102 includes a barrier layer 126, which couldoptionally be a combined adhesion and barrier layer, and a seed layer128 around a conductor core 130. The second channel 104 and the via 106include a barrier layer 132, which could also optionally be a combinedadhesion and barrier layer, and a seed layer 134 around a conductor core136. The barrier layers 126 and 132 are used to prevent diffusion of theconductor materials into the adjacent areas of the semiconductor device.The seed layers 128 and 134 form electrodes on which the conductormaterial of the conductor cores 130 and 136 is deposited. The seedlayers 128 and 134 are of substantially the same conductor material ofthe conductor cores 130 and 136 and become part of the respectiveconductor cores 130 and 136 after the deposition.

[0038] The deposition of the barrier layer 132 is such that it fills thebottom of the via 106 at barrier layer portion 138 so as to effectivelyseparate the conductor cores 130 and 136.

[0039] In the past, for copper conductor material and seed layers,highly resistive diffusion barrier materials such as tantalum nitride(TaN), titanium nitride (TiN), or tungsten nitride (WN) are used asbarrier materials to prevent diffusion. In addition to increasing theoverall resistance of the semiconductor chip which contained all thesemiconductor devices, the barrier region 138 would block diffusion ofcopper from the conductor core 130 to the conductor core 136 aselectromigration caused the movement of copper atoms out of the via 106and allowed the formation of voids therein. Referring now to FIG. 3,therein is shown a cross-section similar to that shown in FIG. 2 (PRIORART) of a semiconductor wafer 200 of the present invention. Thesemiconductor wafer 200 has first and second channels 202 and 204connected by a via 206. The first and second channels 202 and 204 arerespectively disposed in first and second dielectric layers 208 and 210.The via 206 is a part of the second channel 204 and is disposed in a viadielectric layer 212.

[0040] A portion of the first channel 202 is disposed in a first channelstop layer 214 and is on a device dielectric layer 216. Generally, metalcontacts (not shown) are formed in the device dielectric layer 216 toconnect to an operative semiconductor device (not shown). This isrepresented by the contact of the first channel 202 with a semiconductordevice gate 218 embedded in the device dielectric layer 216. The variouslayers above the device dielectric layer 216 are sequentially: the firstchannel stop layer 214, the first channel dielectric layer 208, a viastop layer 220, the via dielectric layer 212, a second channel stoplayer 222, the second channel dielectric layer 210, and a next channelstop layer 224.

[0041] The first channel 202 includes a barrier layer 226 and a seedlayer 228 around a conductor core 230. The second channel 204 and thevia 206 include a barrier layer 232 and a seed layer 234 around aconductor core 236. The barrier layers 226 and 232 are used to preventdiffusion of the conductor materials into the adjacent areas of thesemiconductor device. The seed layers 228 and 234 form electrodes onwhich the conductor material of the conductor cores 230 and 236 isdeposited. The seed layers 228 and 234 are of substantially the sameconductor material of the conductor cores 230 and 236 and become part ofthe respective conductor cores 230 and 236 after the deposition.

[0042] The barrier layer 234 and the seed layer 232 are absent over thesecond channel 202 in the barrier removed region 238 and the seed layerremoved region 240, respectively. To provide conductor material to makeup for any losses due to electromigration from the first channel 202through the via 206 to the second channel 204, a conductor reservoirvolume 245 is provided. In the preferred embodiment, the conductorreservoir volume 245 is an extension placed at the dead end of thehorizontal run of the channel 202 horizontally after the via 206.

[0043] While the conductor reservoir volume 245 can be of any size, thelarger the volume, the longer it will provide protection of theassociated via and channel from electromigration. Thus, the preferredvolume would be one which is equal or greater than the volume of the viawith which it is associated.

[0044] The method for manufacturing the present invention includesdepositing the first dielectric layer 208 over the semiconductor wafer200 on a substrate (not shown) by a deposition process such as chemicalvapor deposition. A first channel opening is etched in the firstdielectric layer 208. The barrier layer 226 is then deposited by aprocess such as chemical vapor deposition to line the first channelopening. The seed layer 228 is then deposited by a process such assputtering to line the barrier layer 226. The seed layer 228 is thenused as an electrode in an electroplating process to fill the firstchannel opening over the barrier layer 226 and seed layer 228 to formthe first channel 202.

[0045] The via stop layer 220 is then deposited over the firstdielectric layer 208 and the first channel 202 and the via dielectriclayer 216 formed on the via stop layer 220 after photolithographprocessing and etching to form a via opening. Subsequent processingforms the second channel stop layer 222 on the via stop layer 220 andthe second dielectric layer 210 on the second channel stop layer 222.

[0046] After photolithographically processing, an etching process isthen used to form a second channel and via opening through the secondchannel dielectric 210, the second channel stop layer 222, the viadielectric layer 216, and the via stop layer 220 to the first channel202. In this process of forming the second channel 204 and via 206, thevia 206 exposes the first channel 202 horizontally away from where thefirst channel 202 dead ends horizontally in FIG. 3. This provides theconductor reservoir volume 245 which is sized to be equal to or largerthan the via 206.

[0047] The barrier layer 232 and the seed layer 234 are then depositedto line the second channel and via opening. The barrier layer 232 in thevia opening over the first channel 202 at the barrier removed region 238and the seed layer 234 in the via opening over the first channel 202 atthe seed layer removed region 240 are then removed. It will beunderstood that, if the barrier layer 232 in the via opening is removedbefore deposition of the seed layer 234, the seed layer does not have tobe removed in the via opening and will become part of the conductor core236.

[0048] A subsequent electroplating process is used to deposit theconductor core 236 to fill the second channel and via opening to formthe second channel 204 and the via 206 and be in electrical contact withthe first conductor core 230.

[0049] The conductor reservoir volume 245 then provides a supply ofconductor material to prevent the formation of voids in the firstchannel and in the via during operation.

[0050] It should be noted that while prior art integrated circuits mayhave volumes which appear to be conductor reservoir volumes, in fact,these are merely volumes which exist because of misalignments of thechannels and vias. Similarly, other documents show what appear to beconductor reservoir volumes, but these are generally due to artisticlicense in rendering interconnects. Those skilled in the art realizethat these volumes do not exist for the purpose of showing the presentinvention which would appear on substantially all channels below vias inan integrated circuit.

[0051] In the best mode, the barrier layers are of materials such astantalum (Ta), titanium (Ti), tungsten (W), nitrides thereof, and acombination thereof. The seed layers and conductor cores are ofmaterials such as copper (Cu), copper-base alloys, aluminum (Al),aluminum-base alloys, gold (Au), gold-base alloys, silver (Ag),silver-base alloys, and a combination thereof. The dielectric layers areof silicon dioxide or a low dielectric material such as HSQ, Flare, etc.The stop layers are of materials such as silicon nitride or siliconoxynitride.

[0052] While the invention has been described in conjunction with aspecific best mode, it is to be understood that many alternatives,modifications, and variations will be apparent to those skilled in theart in light of the aforegoing description. Accordingly, it is intendedto embrace all such alternatives, modifications, and variations thatfall within the spirit and scope of the included claims. All mattershither-to-fore set forth or shown in the accompanying drawings are to beinterpreted in an illustrative and non-limiting sense.

The invention claimed is:
 1. An integrated circuit comprising: asemiconductor substrate having a semiconductor device provided thereon;a first dielectric layer formed over the semiconductor substrate havinga first opening provided therein including a conductor reservoir volume;a first barrier layer lining the first opening; and a first conductorcore filling the first opening and forming a first conductor connectedto the semiconductor device; a second dielectric layer formed over thefirst dielectric layer and having a via and second opening providedtherein; a second barrier layer lining the via and second opening exceptover the first conductor; and a second conductor core filling the viaand second opening to form a via and second conductor having the viaproximate the conductor reservoir volume whereby conductor materialmigrates during operation due to electromigration from the conductorreservoir volume into the via and second conductor.
 2. The integratedcircuit as claimed in claim 1 wherein the volume of the conductorreservoir volume is sized to equal the volume of the via conductor. 3.The integrated circuit as claimed in claim 1 wherein the volume of theconductor reservoir volume is sized to exceed the volume of the viaconductor.
 4. The integrated circuit as claimed in claim 1 wherein thebarrier layer is of a material selected from a group consisting oftantalum, titanium, tungsten, nitrides thereof, and a combinationthereof.
 5. The integrated circuit as claimed in claim 1 wherein theconductor core contains a material selected from a group consisting ofcopper, copper-base alloys, aluminum, gold, gold-base alloys, silver,silver-base alloys, and a combination thereof.
 6. An integrated circuitcomprising: a silicon substrate having semiconductor devices providedthereon; a device oxide layer formed over the silicon substrate; a firstchannel oxide layer formed over the device oxide layer having aplurality of first channel openings provided therein including aplurality of conductor reservoir volume; a first barrier layer liningthe first channel opening; first conductor cores filling the pluralityof first channel openings and forming a plurality of first channelsconnected to the semiconductor devices; a second channel oxide layerformed over the first channel oxide layer and having a plurality ofsecond channel and via openings provided therein; a second barrier layerlining the second channel and via openings except over the plurality offirst channels; second conductor cores filling the plurality of secondchannel and via openings to form a plurality of vias and second channelswhereby conductor material migrate in operation due to electromigrationfrom the conductor reservoir volumes into the plurality of vias.
 7. Theintegrated circuit as claimed in claim 6 wherein the volume of each ofthe plurality of the conductor reservoir volumes is sized to equal thevolume of each of the plurality of associated vias.
 8. The integratedcircuit as claimed in claim 6 wherein the volume of each of theplurality of the conductor reservoir volumes is sized to exceed thevolume of each of the plurality of associated vias.
 9. The integratedcircuit as claimed in claim 6 wherein the barrier layers contain a metalselected from a group consisting of tantalum, titanium, tungsten, and acombination thereof.
 10. The integrated circuit as claimed in claim 6wherein the conductor cores contain a material selected from a groupconsisting of copper, copper-base alloys, aluminum, aluminum-basealloys, gold, gold-base alloys, silver, silver-base alloys, and acombination thereof.
 11. A method of manufacturing an integrated circuitcomprising: providing a semiconductor substrate having a semiconductordevice provided thereon; forming a dielectric layer on the semiconductorsubstrate; forming a opening in the dielectric layer including aconductor reservoir volume; depositing a barrier layer to line theopening; depositing a first conductor core over the barrier layer tofill the opening including the conductor reservoir volume and connect tothe semiconductor device forming a second dielectric layer over thefirst dielectric layer; forming a via and second opening in the seconddielectric layer, the via opening open to the first conductor coreadjacent to the conductor reservoir volume; depositing a second barrierlayer to line the via and second opening except over the firstconductor; and depositing a second conductor core to fill the via andsecond opening to form a via and second conductor having the viaproximate the conductor reservoir volume whereby conductor materialmigrates during operation due to electromigration from the conductorreservoir volume into the via and second conductor.
 12. The method ofmanufacturing an integrated circuit as claimed in claim 11 wherein theforming the opening includes forming the conductor reservoir volume tohave a volume equal to the volume of the via.
 13. The method ofmanufacturing an integrated circuit as claimed in claim 11 wherein theforming the opening includes forming the conductor reservoir volume tohave a volume which exceeds the volume of the via.
 14. The method ofmanufacturing an integrated circuit as claimed in claim 11 wherein thedepositing the barrier layer deposits a material selected from a groupconsisting of tantalum, titanium, tungsten, nitrides thereof, and acombination thereof.
 15. The method of manufacturing an integratedcircuit as claimed in claim 11 wherein the depositing the conductor coredeposits a material selected from a group consisting of copper,copper-base alloys, aluminum, gold, gold-base alloys, silver,silver-base alloys, and a combination thereof.
 16. A method ofmanufacturing an integrated circuit comprising: providing a siliconsubstrate having semiconductor devices provided thereon; forming adevice oxide layer over the silicon substrate; forming a first oxidelayer on the device oxide layer; forming a plurality of first channelopenings in the first oxide layer including a plurality of conductorreservoir volumes; depositing a barrier layer to line the plurality offirst channel openings; depositing a first conductor layer over thebarrier layer to fill the plurality of first channel openings includingthe plurality of conductor reservoir volumes and connect to thesemiconductor devices through the device oxide layer; removing the firstconductor and barrier layer over the first oxide layer to form aplurality of first channels; forming a second dielectric layer over thefirst dielectric layer; forming a plurality of via and second openingsin the second dielectric layer, the via openings each open to the one ofthe plurality of first channels and adjacent to one of the plurality ofconductor reservoir volumes; depositing a second barrier layer to linethe plurality of via and second openings except over the plurality offirst channels; and depositing a second conductor layer to fill the viaand second opening and in contact with the first channel; removing thesecond conductor and second barrier layers over the second oxide layerto form a plurality of vias and second channels connected to theplurality of first channels by the plurality of vias proximate to theplurality of conductor reservoir volumes whereby conductor materialmigrate during operation due to electromigration from the plurality ofconductor reservoir volumes into the plurality of vias.
 17. The methodof manufacturing an integrated circuit as claimed in claim 16 whereinthe depositing forming the plurality of first channel openings form theplurality of conductor reservoir volumes to be equal to the volumes ofthe plurality of vias.
 18. The method of manufacturing an integratedcircuit as claimed in claim 16 wherein the depositing forming theplurality of first channel openings form the plurality of conductorreservoir volumes to exceed to the volumes of the plurality of vias. 19.The method of manufacturing an integrated circuit as claimed in claim 16wherein the depositing the barrier layer contains a metal selected froma group consisting of tantalum, titanium, tungsten, and a combinationthereof.
 20. The method of manufacturing an integrated circuit asclaimed in claim 16 wherein the depositing the conductor core depositsthe metal selected from a group consisting of copper, copper-basealloys, aluminum, aluminum-base alloys, gold, gold-base alloys, silver,silver-base alloys, and a combination thereof.